A synchronous digital hierarchy (SDH) for transmitting asynchronous signals in a multiplexed form in a synchronization frame has been standardized as recommended by CCITT (International Telegraph and Telephone Consultative Committee) and T1 Committee of U.S.A. In the synchronous digital hierarchy, it is necessary to extract asynchronous signals from the received signals in order to obtain valid data accompanying almost no jitter.
In the synchronous digital hierarchy (SDH) recommended by CCITT, a difference in speed between the synchronous system and the asynchronous system is corrected by a pointer adjustment function; i.e., invalid data consisting of eight bits is inserted or deleted by the pointer adjustment, and a phase jump of eight bits takes place in the formation payload. The phase jump causes jitter that is given to asynchronous signals extracted from the synchronous multiplexed signals that are received. On the receiving side, therefore, the jitter must be suppressed by using phase-locked loop circuit or a like circuit.
On the receiving side in the conventional synchronous digital hierarchy as will be described later in detail, valid data only are written using a buffer memory when the asynchronous signals are to be extracted by receiving synchronous multiplex signals, and the valid data are read out according to read clock signals. Here, the write clock signals of a buffer memory have an untoothed period that varies depending upon the presence or absence of pointer adjustment, and the moment at which the pointer adjustment takes place is not definite, resulting in the occurrence of low-frequency jitter as described above.
As a means for reducing the low-frequency jitter, for example, the Contribution (T1X1.6/89-020R2) of T1X1.6 of U.S.A. discloses circuits and problems. The circuits are:
(1) A desynchronizer (asynchronous signal extracting circuit) equipped with a PLL of a very low frequency band;
(2) A synchronous desynchronizer;
(3) A fixed bit leak circuit (using PLLs in two stages); and
(4) A two-stage PLL of the linear digital control type.
The circuit (1) requires a PLL of a frequency band as narrow as about 3 Hz with which it is difficult to realize a practical circuit.
The circuit (2) requires digital control that adapts to the monitoring of a buffer memory, which results in a complex circuit apparatus and control operation.
In the circuit (3), the bits slowly leak over a given period of time as the pointer adjustment takes place, and the jitter component decreases. Here, however, the buffer memory must have an extra capacity to cope with the pointer adjustment that takes place continuously.
The circuit (4) requires a digital filter or a dither, causing the circuit apparatus to become complex.